Archive for verification

You are browsing the archives of verification.

How many DFT Engineers are there, really?

I sometimes wonder this.
It seems in the past several years, the design-for-test job has grown more complicated (as any other facet of the electronics design discipline), what with new (or more prominent) defect mechanisms and fault models, and new DFT methods and technologies to address them.
I was reading an interview at T&M World with Atun [...]

DATE 2008 – Starts Today!

Good day DFT folk – just a reminder, DATE 2008 started today. For those of you readers who are lucky enough to be in Munich this week for the event: What are you looking for? What sessions, and/or events do you have your eye on?
One person there this week is JL Gray of [...]

Test and Verification: Quid Pro Quo

I was reading Peggy Aycinena’s DVCON post at EDACafe this past week, and ran across a couple of thought provoking (at least for me) paragraphs. Ms. Aycinena was describing the Wednesday keynote speech given by Wally Rhines [...]